8051SBC USB & GLCD Expansion Board

8051SBC USB &  GLCD Expansion Board8051SBC USB & GLCD Expansion Board Hardware Schematic

Hardware Schematic

J2 is 24-pin header, you may see the signals on J2, it provides necessary signals for memory mapped I/O expansion. Those signals include:

Data bus: D0-D7,
Address bus: A0-A4, A8,A9,A10, and A15,
Control bus: /RD, /WR, RESET, /INT0, /INT1,
Power supply: +5V and GND.

The data bus, D0-D7 signals are tied to both FT245BM and GLCD data bus directly.
The enable signal for USB chip and GLCD controller were made by PLD decoder from the address lines. As we have seen the memory map for i/o of 8051SBC board, the available space is from 0x0300-0x07FF. The address range of 0x0300-0x03FF was used for USB chip for both RD and WRITE operations. The GLCD used 0x0400-0x04FF with A0-A3 for selecting the internal registers from 0x0404-0x040B.

We have learned from 8051SBC on how to use PLD as the memory decoder. In the schematic you may see the equivalent logic symbol for each enable signal. Let study the logic equation shown in Figure 3 and the equivalent logic circuit, you will understand how easy it is.

; USB8051SBC PLD Equation
; Memory and I/O decoder for USB&GLCD expansion Board
; Wichit Sirichote,
; Dec 13, 2003
; PLD: Lattice GAL16V8D

a15=1 rd=2 wr=3 a8=4 a9=5 a10=6 glcd_enable=17 rd_usb=18 wr_usb=19 RST=7 LCD_RST=16


/glcd_enable = rd * wr + a8 + a9 + /a10 + a15

/wr_usb = /a8 + /a9 + a10 + a15 + wr

rd_usb = /a8 + /a9 + a10 + a15 + rd


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