1.2GHz Voltage Controlled Oscillator With Linear Modulation

1.2GHz Voltage Controlled Oscillator With Linear Modulation

Since high frequency voltage-controlled oscillators, or VCOs, are not easy to construct, Maxim (www.maxim-ic.com) has produced an integrated 1.2GHz oscillator, the MAX2754. The center frequency is set using the TUNE input, and a linear modulation input allows the frequency to be modulated. The IC is available in an 8-pin µMAX package, operates from a supply of between 2.7 V and 5.5 V, and draws a current of less than 2 mA. Both TUNE and MOD operate over control voltage range of +0.4 V to +2.4 V. TUNE allows the VCO frequency to be adjusted from 1050 MHz to 1270 MHz. In some applications a PLL control voltage will be applied here, allowing the center frequency to be set exactly to a desired value. For simplicity in the circuit diagram we have shown a potentiometer. The MOD input allows the VCO to be modulated in a digital or analogue fashion, with a transfer slope of –500 kHz/V. In the circuit we have shown an example where MOD is used for frequency shift keying (FSK) modulation. Resistors R1 to R4 shift the level of the data signal so that it has a center value of +1.4 V and an amplitude corresponding to the desired frequency deviation. One example set of values, suitable for use with a 5 V power supply, is as follows: R1 = 480 Ω, R2 = 100 Ω, R3 = 220 Ω und R4 = 270 Ω.

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Small Power Transformer Telephone Ring Generator

This ring generator will ring a telephone once every 10 seconds. The interval between rings can be lengthened or shortened by varying the value of the 1 Meg resistor. The 70 volt/ 30 Hz ring voltage is produced from the 120 volt side of a small 12.6 VAC power transformer (Radio Shack 273-1365). Both capacitors connected across the transformer windings are non-polarized / 100 volts. Circuit draws about 300mA from the 12 volt DC power supply during the ringing interval.

Small Power Transformer Telephone Ring Generator Circuit

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1 Second Time Base From Crystal Oscillator

1 Second Time Base From Crystal Oscillator

The schematic below illustrates dividing a crystal oscillator signal by the crystal frequency to obtain an accurate (0.01%) 1 second time base. Two cascaded 12 stage counters (CD4040) form a 24 stage binary counter and the appropriate bits are gated together to produce the desired division. Using a crystal of some even multiple of 2 is desirable so that one stage of the counter automatically toggles every second which eliminates the need for the NAND gate and reset circuitry, however the circuit below illustrates using a crystal which is not an even multiple of 2 and so requires additional components.

Using a 50 Khz crystal, a count of 50000 is detected when the appropriate counter bits that add up to 50000 are all high. This corresponds to bits 15 (32768) + 14 (16384) + 9 (512) + 8 (256) + 6 (64) + 4 (16). Bits 14 and 15 are the 3rd and 4th stages of the second counter, bit 0 is the first stage of the first counter (Q1, pin 9). To use a 100 Khz crystal, each bit would be moved one to the right so the total would be (65536 + 32768 + 1024 + 512 + 128 + 32 = 100,000). Using a 1 Mhz crystal, the following bits would be needed:

Bit 19 - Right counter - Q8 - pin 13  -  Decimal value = 524288
   18                    7        4                     262144
   17                    6        2                     131072
   16                    5        3                      65536
   14                    3        6                      16384
    9 - Left counter  - 10       14                        512
    6                    7        4                         64
                                                      ---------
                                                      1,000,000

At 1 Mhz, the 330K resistor in the oscillator circuit will need to be reduced proportionally to about 15K. When the terminal count is reached, a 7 uS reset pulse is generated by the Schmitt Trigger inverter stage that follows the NAND gate. The 47K resistor and 470 picofarad capacitor sustain the output so that the counters are reliably reset to zero. This is less than one clock cycle at 50Khz and does not introduce an error but would amount to 7 cycles at 1 MHz which would cause the counters to lose 7 microseconds of time per second. It's not much of an error (7 parts in a million) but it would be there. The minimum reset pulse width for the 4040 CMOS counters is about 1.5 uS, so the reset pulse cannot be made much shorter.

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